Method and device for testing of an integrated circuit

ABSTRACT

A method for testing an integrated circuit that has a testing portion for testing the circuit card and/or other circuits connected to the integrated circuit after the integrated circuit has been assembled onto the circuit card, inputs for controlling the testing portion, and test structures for testing the internal operations of the integrated circuit. To keep the number of the inputs to the circuit low, a test mode is defined for the testing portion, in which test mode one of the inputs of the testing portion is connected to the test structures for the internal operations of the integrated circuit, and when the internal operations of the integrated circuit are tested, the testing portion is set in the test mode, whereupon the internal test structures of the integrated circuit can be controlled from the input of the testing portion.

This application is a 371 of PCT/FI94/00439 filed Sep. 30, 1994.

BACKGROUND OF THE INVENTION

The invention relates to a method for testing an integrated circuit, thecircuit comprising testing means for testing the circuit card and/orother circuits connected to the integrated circuit after it has beenassembled onto the circuit card, inputs for controlling the testingmeans, and test structures for testing the internal operations of theintegrated circuit. The invention also relates to an integrated circuit,comprising testing means for testing the circuit card and/or othercircuits connected to the integrated circuit after it has been assembledonto the circuit card, inputs for controlling the testing means, andtest structures for testing the internal operations of the integratedcircuit.

The invention relates in particular to the testing of the internaloperation of an ASIC circuit conducted by a circuit manufacturer inconnection with the manufacturing. The aim of this test is to check theoperation of the circuits by feeding test data into the inputs of thecircuit, after which signals obtained from the outputs of the circuitare monitored. To conduct these tests, so-called scan path teststructures have been formed in the circuit during its manufacturing, thetest structures being intended solely for in-circuit testing. A separatepin, i.e. an input port, is reserved in the circuit for controlling thescan path test structures. Said pin has proved to be very problematic,since fitting it in the integrated circuit often calls for the use of alarger housing. Scan path testing is described, for example, in DigitalSystems Testing and Testable Design (by M. Abramovic, M. A. Breuer & A.D. Friedman, Computer Science Press, New York, USA), and therefore it isnot described in greater detail in this connection.

In addition to the testing of the internal operation of a singleintegrated circuit, the entire circuit card onto which the integratedcircuit is assembled is also usually tested. For this purpose, testlogic needed in particular for this type of testing is built into theintegrated circuits. For example, in the ASIC circuits, it is possibleto use boundary scan blocks according to the IEEE Standard (TheInstitute of Electrical and Electronics Engineers, Inc.) 1149.1, theblocks being applicable, among other things, in testing the connectionsbetween components assembled onto the circuit board. For the purpose ofconducting these tests, the ASIC circuits comprise special pins, i.e.input ports, for controlling the tests.

With an increasing demand for smaller and smaller integrated circuits,it has proved to be necessary to limit the number of pins, i.e. inputsand outputs, in the circuits, since in practice they have a verysignificant effect on the size of the housing of the integrated circuit.The use of a larger housing may in turn lead into situations, where thesize of that circuit card onto which the integrated circuit is to beassembled is too small, wherefore a larger circuit card has to be used.

SUMMARY OF THE INVENTION

The purpose of this invention is to provide a method by means of whichthe internal structures of an integrated circuit can be tested without,for enabling the testing, having to add extra pins to the circuit. Theseaims are achieved with a method according to the invention, which ischaracterized in that a test mode is defined for the testing means, inwhich test mode one of the inputs of the testing means is connected tothe test structures for the internal operations of the integratedcircuit, and that when the internal operations of the integrated circuitare tested, the testing means are set in the test mode, whereupon theinternal test structures of the integrated circuit can be controlledfrom the input of the testing means.

The invention is based on the idea that when the test structuresrequired for testing the internal operations of the circuit areconnected with the testing means intended for the testing of theconnections between the circuits on the circuit board in such a way thata mode where one of the inputs of the testing means is connected to theinternal test structures is defined for the testing means, it is notnecessary to provide the integrated circuit with a separate pin, i.e. aninput, for controlling the internal test structures. Therefore, the sizeof the housing of the integrated circuit can be decreased, and inaddition to this, the in-circuit testing becomes faster, since thesolution according to the invention makes it possible to testsimultaneously several scan paths. The greatest advantage of the methodaccording to the invention is therefore that it saves space, since thenumber of pins in the integrated circuit decreases, which thusconsiderably diminishes the size of the circuit. It is also easy todefine several modes for the testing means for testing independently theinternal structures of different blocks.

The invention also relates to an integrated circuit, where the methodaccording to the invention can be applied. The circuit according to theinvention is characterized in that at least one of the inputs of thetesting means is connected to the input of a switching device, which iscontrolled by means of the testing means, and that a test mode isdefined for the testing means, in which mode the switching device allowsdata fed into its input to propagate from its output, and that theoutput of the switching device is connected to the test structures ofthe internal operations of the integrated circuit, whereupon the teststructures of the internal operations can be controlled from the inputof the testing means by setting the testing means in the test mode.

The major advantages of the integrated circuit according to theinvention are thus that the circuit requires fewer pins (inputs/outputs)for testing purposes than known circuits, wherefore the size of thecircuit can be decreased and there is no need to control any "extra"pins during the normal operation of the circuit, and that it is fasterto test the internal structures of the circuit than in known circuits.

BRIEF DESCRIPTION OF THE DRAWING

The invention will be described in the following in greater detail withreference to the accompanying drawing, in which: The figure is a blockdiagram of a preferred embodiment of the integrated circuit according tothe invention.

DETAILED DESCRIPTION

The ASIC circuit 1 shown in the figure comprises a boundary scan block 2according to the IEEE Standard (The Institute of Electrical andElectronics Engineers, Inc.) 1149.1, the block being applicable, amongother things, in testing the connections between the components on thecircuit card after the ASIC circuit shown in the figure is assembledonto the circuit board. The boundary scan block 2 comprises three inputs7, 12 and 13, and each of them is connected to one of the pins of theASIC circuit. The TMS input 12 (test mode select input) is used forselecting the test mode, a clock pulse is fed into the TCK input 13(test clock input), and serial data required for conducting the test isfed from the TDI port 7 (test data input). The testing operation iscontrolled by means of data obtained from the aforementioned inputs anddecoded by a TAP (test access port) controller 11.

The output of the TAP controller 11 is connected to the input of aninstruction register (IR) 3. The instruction register is used to selectthe test to be performed. A decoding block 4 (IR Decoding) of theinstruction register is connected to the output of the instructionregister, the instruction obtained from the instruction register beinginterpreted and carried out by means of the decoding block. Thecouplings by means of which the connections between the components onthe circuit board are tested are not shown in the figure. The operationof the boundary scan block 2 is described in greater detail in thestandard IEEE-1149.1 IEEE Standard Test Access Port and Boundary ScanArchitecture (IEEE, 1990, New York, USA).

For the purpose of testing the internal structures of the ASIC circuit1, the circuit shown in the figure comprises a scan path test structure,intended solely for testing the internal operation of the circuit. Thetest conducted by means of the scan path is controlled by means of itscontrol input 6. Scan path testing is described for example in DigitalSystems Testing and Testable Design (by M. Abramovic, M. A. Breuer & A.D. Friedman, Computer Science Press, New York, USA), and therefore it isnot described in greater detail in this connection.

For the purpose of testing the internal structures of the ASIC circuit1, one private instruction defined in the IEEE Standard 1149.1 isreserved in the instruction register 3 of the boundary scan block 2shown in the figure for controlling the scan path of the ASIC circuit 1;that instruction will hereafter be called the scan mode.

When the scan mode has been selected from the instruction register, thatoutput 14 in the decoding block 4 of the instruction register whichindicates the scan mode is activated, i.e. it is given the value "1". Inother instruction modes, i.e. when the internal operation of the ASICcircuit is not being tested, the value of the output 14 is "0".

Due to an AND gate 5 placed between the decoding block 4 and the controlinput 6 of the scan path of the ASIC circuit, the control input 6remains inactive as long as the output 14 indicating the scan mode is inthe passive state. Thus it is ensured that the control input 6 remainsinactive during the normal operation of the circuit 10 and during othertest modes of the boundary scan block 2. Then the TDI input 7 is usedfor feeding serial test data, wherefore feeding this test datasimultaneously through the control input 6 could lead into errorsituations.

When the output 14 indicating the scan mode acquires the value "1" afteran instruction for the scan mode has been given, the AND circuit 5 isactivated, whereupon a control signal supplied from the TDI port 7 canpropagate to the control input 6 of the scan mode. Thus the internaltesting of the ASIC circuit 1 can be controlled directly by means of theTDI port 7 (test data input), i.e. the testing can be controlled by theinput 7 of the boundary scan block 2, and therefore it is not necessaryto provide a separate pin (input) in the ASIC circuit 1 for thispurpose.

One of the normal inputs of the ASIC circuit, for example input 8, isused as the scan input required by the scan path structure, as shown inthe figure. The output of some flip-flop in the scan path is used inturn directly as the scan output required by the scan path structure,for example output 9, as shown in the figure, if it is an output portdirectly outbound from the circuit 10. If a direct output port of thecircuit cannot be selected as the scan output in the scan path, the scanoutput can be directed to one of the output ports of the circuit bymeans a multiplexer (not shown in the figure).

It must be understood that the appended description and the figurerelated thereto describe only one preferred embodiment according to theinvention. Therefore, for example the method according to the inventioncan also be applied in other integrated circuits and not only in ASICcircuits, even though the invention is described -above mainly inconnection with ASIC circuits. The preferred embodiments of the methodand the integrated circuit according to the invention can thus bemodified within the scope of the appended claims.

I claim:
 1. A method of testing an integrated circuit after theintegrated circuit has been assembled, together with other components,onto a circuit card, the integrated circuit having test structures fortesting internal operations of the integrated circuit, said integratedcircuit having at least one input for inputting test data to theintegrated circuit and at least one output for outputting results fromtesting of internal operation of the integrated circuit,said methodcomprising: providing a testing block having at least one mode in whichis operable for testing said circuit card and/or at least one of saidother components, said testing block having at least one input forcontrolling said testing block, and an output normally effectivelyisolated from, but effectively connected in a test state to said teststructures; providing a signal via said at least one input of saidtesting block to said testing block for initiating said test state andthereby effectively connecting said testing block to said teststructures of said integrated circuit; and controlling said internaltest structures of said integrated circuit by providing signals via saidat least one input of said testing block to said internal teststructures of said integrated circuit, while supporting test data tosaid integrated circuit via said at least one input of said integratedcircuit, and monitoring said at least one output of said integratedcircuit.
 2. Apparatus for testing an integrated circuit after theintegrated circuit has been assembled, together with other components,onto a circuit card, the integrated circuit having test structures fortesting internal operations of the integrated circuit, said integratedcircuit having at least one input for inputting test data to theintegrated circuit and at least one output for outputting results fromtesting of internal operation of the integrated circuit,said apparatuscomprising: testing block having at least one mode in which is operablefor testing said circuit card and/or at least one of said othercomponents, said testing block having at least one input for controllingsaid testing block, and an output normally effectively isolated from,but effectively connected in a test state to said test structures; saidat least one input of said testing block being arranged for sending asignal for initiating said test state and thereby effectively connectingsaid testing block to said test structures of said integrated circuit;and said testing block being arranged for controlling said internal teststructures of said integrated circuit by providing signals via said atleast one input of said testing block to said internal test structuresof said integrated circuit, while test data is supplied to saidintegrated circuit via said at least one input of said integratedcircuit, and said at least one output of said integrated circuit ismonitored for test results.
 3. The apparatus of claim 2 wherein:saidintegrated circuit is a synchronous ASIC.
 4. The apparatus of claim 2wherein:said at least one input of said testing block includes a firstinput, a second input and a third input; said first input being arrangedto provide a clock pulse; said second input being arranged to providedata indicating choice between said at least one mode and said teststate; and said third input being arranged to provide test data; andsaid testing block further includes an instruction register which isarranged to select which of a plurality of tests is to be conducted,based on signals received via said at least one in put of said testingblock.
 5. The apparatus of claim 4 wherein:said integrated circuit is asynchronous ASIC.